|
If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
Datasheet File OCR Text: |
rev. 2.5 april 2003 1/153 st72334j/n, st72314j/n, st72124j 8-bit mcu with single voltage flash memory, adc, 16-bit timers, spi, sci interfaces n memories C 8k or 16k program memory (rom or single voltage flash) with read-out protection and in-situ programming (remote isp) C 256 bytes eeprom data memory (with r ead- out protection option in rom devices) C 384 or 512 bytes ram n clock, reset and supply management C enhanced reset system C enhanced low voltage supply supervisor with 3 programmable levels C clock sources: crystal/ceramic resonator os- cillators or rc oscillators, external clock, backup clock security system C 4 power saving modes: halt, active-halt, wait and slow C beep and clock-out capabilities n interrupt management C 10 interrupt vectors plus trap and reset C 15 external interrupt lines (4 vectors) n 44 or 32 i/o ports C 44 or 32 multifunctional bidirectional i/o lines: C 21 or 19 alternate function lines C 12 or 8 high sink outputs n 4 timers C configurable watchdog timer C realtime base C two 16-bit timers with: 2 input captures (only one on timer a), 2 output compares (only one on timer a), external clock input on timer a, pwm and pulse generator modes n 2 communications interfaces C spi synchronous serial interface C sci asynchronous serial interface (lin com- patible) n 1 analog peripheral C 8-bit adc with 8 input channels (6 only on st72334jx, not available on st72124j2) n instruction set C 8-bit data manipulation C 63 basic instructions C 17 main addressing modes C 8 x 8 unsigned multiply instruction C true bit manipulation n development tools C full hardware/software development package device summary tqfp44 10 x 10 psdip42 psdip56 tqfp64 14 x 14 features st72124j2 st72314j2 st72314j4 st72314n2 st72314n4 st72334j2 st72334j4 st72334n2 st72334n4 program memory - bytes 8k 8k 16k 8k 16k 8k 16k 8k 16k ram (stack) - bytes 384 (256) 384 (256) 512 (256) 384 (256) 512 (256) 384 (256) 512 (256) 384 (256) 512 (256) eeprom - bytes - - - -- 256 256 256 256 peripherals watchdog, two 16-bit timers, spi, sci -adc operating supply 3.2v to 5.5 v cpu frequency up to 8 mhz (with up to 16 mhz oscillator) operating temperature -40c to +85c (-40c to +105/125c optional) packages tqfp44 / sdip42 tqfp64 / sdip56 tqfp44 / sdip42 tqfp64 / sdip56 1
table of contents 153 2/153 2 1 preamble: st72c334 versus st72e331 specification . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 5 flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 5.3 structural organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.4 in-situ programming (isp) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.5 memory read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 data eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 6.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 6.3 memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.4 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.5 access error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 data eeprom register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.1 read-out protection option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 8.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 8.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.1 low voltage detector (lvd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.2 reset sequence manager (rsm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.3 multi-oscillator (mo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.4 clock security system (css) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.5 supply, reset and clock register description . . . . . . . . . . . . . . . . . . . . . 32 10 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.1 non maskable software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.2 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.3 peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11.2 slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11.3 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11.4 active-halt and halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 12 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.3 i/o port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table of contents 3/153 3 12.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 12.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 13 miscellaneous registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 13.1 i/o port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 13.2 i/o port alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 13.3 registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 14 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 14.1 watchdog timer (wdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 14.2 main clock controller with real time clock timer (mcc/rtc) . . . . . . . 52 14.3 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 14.4 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 14.5 serial communications interface (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 14.6 8-bit a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 15 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 15.1 st7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 15.2 instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 16 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 16.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 16.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 16.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 16.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 16.5 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 16.6 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 16.7 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 16.8 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 16.9 control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 16.10 timer peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 16.11 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 135 16.12 8-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 17 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 17.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 17.2 soldering and glueability information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 18 device configuration and ordering information . . . . . . . . . . . . . . . . . . . . . . . 144 18.1 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 44 18.2 transfer of customer code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 18.3 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 18.4 st7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 19 important notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 19.1 sci baud rate registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 20 summary of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 st72334j/n, st72314j/n, st72124j 4/153 to obtain the most recent version of this datasheet, please check at www.st.com>products>technical literature>datasheet. please also pay special attention to the section important notes on page 151 st72334j/n, st72314j/n, st72124j 5/153 1 preamble: st72c334 versus st72e331 specification new features available on the st72c334 n 8 or 16k flash/rom with in-situ programming and read-out protection n new adc with a better accuracy and conversion time n new configurable clock, reset and supply system n new power saving mode with real time base: active halt n beep capability on pf1 n new interrupt source: clock security system (css) or main clock controller (mcc) st72c334 i/o configuration and pinout n same pinout as st72e331 n pa6 and pa7 are true open drain i/o ports without pull-up (same as st72e331) n pa3, pb3, pb4 and pf2 have no pull-up configuration (all i/os present on tqfp44) n pa5:4, pc3:2, pe7:4 and pf7:6 have high sink capabilities (20ma on n-buffer, 2ma on p-buffer and pull-up). on the st72e331, all these pads (except pa5:4) were 2ma push-pull pads without high sink capabilities. pa4 and pa5 were 20ma true open drains. new memory locations in st72c334 n 20h: miscr register becomes miscr1 register (naming change) n 29h: new control/status register for the mcc module n 2bh: new control/status register for the clock, reset and supply control. this register replaces the wdgsr register keeping the wdogf flag compatibility. n 40h: new miscr2 register st72334j/n, st72314j/n, st72124j 6/153 2 introduction the st72334j/n, st72314j/n and st72124j de- vices are members of the st7 microcontroller fam- ily. they can be grouped as follows: C st72334j/n devices are designed for mid-range applications with data eeprom, adc, spi and sci interface capabilities. C st72314j/n devices target the same range of applications but without data eeprom. C st72124j devices are for applications that do not need data eeprom and the adc peripher- al. all devices are based on a common industry- standard 8-bit core, featuring an enhanced instruc- tion set. the st72c334j/n, st72c314j/n and st72c124j versions feature single-voltage flash memory with byte-by-byte in-situ pro- gramming (isp) capability. under software control, all devices can be placed in wait, slow, active-halt or halt mode, reducing power consumption when the application is in idle or standby state. the enhanced instruction set and addressing modes of the st7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. in addition to standard 8-bit data management, all st7 micro- controllers feature true bit manipulation, 8x8 un- signed multiplication and indirect addressing modes. for easy reference, all parametric data are located in section 16 on page 107 . figure 1. general block diagram 8-bit core alu address and data bus osc1 ispsel control program (8k or 16k bytes) v ss reset port f pf7,6,4,2:0 (6-bit) timer a beep port a ram (384 or 512 bytes) port c 8-bit adc v dda v ssa port b pb7:0 port e pe7:0 sci timer b pa7:0 port d pd7:0 spi pc7:0 (8-bit) v dd eeprom (256 bytes) watchdog multi osc lvd osc2 memory mcc/rtc + clock filter (8-bit for n versions) (5-bit for j versions) (8-bit for n versions) (5-bit for j versions) (6-bit for n versions) (2-bit for j versions) (8-bit for n versions) (6-bit for j versions) st72334j/n, st72314j/n, st72124j 7/153 3 pin description figure 2. 64-pin tqfp package pinout (n versions) v dda v ssa v dd_3 v ss_3 mco / pf0 beep / pf1 pf2 nc ocmp1_a / pf4 nc icap1_a / (hs) pf6 extclk_a / (hs) pf7 ain4 / pd4 ain5 / pd5 ain6 / pd6 ain7 / pd7 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ei2 ei3 ei0 ei1 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 ain0 / pd0 ain1 / pd1 ain2 / pd2 ain3 / pd3 (hs) pe4 (hs) pe5 (hs) pe6 (hs) pe7 pa1 pa0 pc7 / ss pc6 / sck / ispclk pc5 / mosi pc4 / miso / ispdata pc3 (hs) / icap1_b pc2 (hs) / icap2_b pc1 / ocmp1_b pc0 / ocmp2_b v ss_0 v dd_0 v ss_1 v dd_1 pa3 pa2 v dd _2 osc1 osc2 v ss _2 nc nc reset ispsel pa7 (hs) pa6 (hs) pa5 (hs) pa4 (hs) nc nc pe1 / rdi pe0 / tdo (hs) 20ma high sink capability ei x associated external interrupt vector st72334j/n, st72314j/n, st72124j 8/153 pin description (contd) figure 3. 56-pin sdip package pinout (n versions) 52 51 50 49 48 47 46 45 44 43 42 41 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 53 54 55 56 pb4 pb5 beep / pf1 mco / pf0 v ssa v dda ain7 / pd7 ain6 / pd6 ain5 / pd5 ain2 / pd2 ain1 / pd1 ain0 / pd0 pb7 pb6 ain4 / pd4 ain3 / pd3 pb3 pb2 ispsel reset v ss _2 osc2 osc1 v dd _2 pe0 / tdo pe5 (hs) pe6 (hs) pe7 (hs) pb0 pb1 pe4 (hs) pe1 / rdi ei3 ei0 ei2 ei1 21 20 17 18 19 v dd_0 extclk_a / (hs) pf7 icap1_a / (hs) pf6 ocmp1_a / pf4 pf2 40 39 38 37 36 v ss_1 pa4 (hs) pa5 (hs) pa6 (hs)i pa7 (hs) 23 22 ocmp2_b / pc0 v ss_0 28 27 24 25 26 mosi / pc5 ispdata/ miso / pc4 icap1_b / (hs) pc3 icap2_b / (hs) pc2 ocmp1_b / pc1 35 34 pa3 v dd_1 33 32 31 30 29 pc6 / sck / ispclk pc7 / ss pa0 pa1 pa2 (hs) 20ma high sink capability ei x associated external interrupt vector st72334j/n, st72314j/n, st72124j 9/153 pin description (contd) figure 4. 44-pin tqfp and 42-pin sdip package pinouts (j versions) mco / pf0 beep / pf1 pf2 ocmp1_a / pf4 icap1_a / (hs) pf6 extclk_a / (hs) pf7 v dd_0 v ss_0 ain5 / pd5 v dda v ssa 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 ei2 ei3 ei0 ei1 pb3 pb4 ain0 / pd0 ain1 / pd1 ain2 / pd2 ain3 / pd3 ain4 / pd4 pe1 / rdi pb0 pb1 pb2 pc6 / sck / ispclk pc5 / mosi pc4 / miso / ispdata pc3 (hs) / icap1_b pc2 (hs) / icap2_b pc1 / ocmp1_b pc0 / ocmp2_b v ss_1 v dd_1 pa3 pc7 / ss v ss _2 reset ispsel pa7 (hs) pa6 (hs) pa5 (hs) pa4 (hs) pe0 / tdo v dd _2 osc1 osc2 38 37 36 35 34 33 32 31 30 29 28 27 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 39 40 41 42 pb4 ain0 / pd0 ocmp2_b / pc0 extclk_a / (hs) pf7 icap1_a / (hs) pf6 ocmp1_a / pf4 pf2 beep / pf1 mco / pf0 ain5 / pd5 ain4 / pd4 ain3 / pd3 ain2 / pd2 ain1 / pd1 v ssa v dda pb3 pb2 pa4 (hs) pa5 (hs) pa6 (hs) pa7 (hs) ispsel reset v ss _2 v dd _2 pe0 / tdo pe1 / rdi pb0 pb1 osc1 osc2 ei3 ei0 ei2 ei1 21 20 17 18 19 mosi / pc5 ispdata / miso / pc4 icap1_b / (hs) pc3 icap2_b/ (hs) pc2 ocmp1_b / pc1 26 25 24 23 22 pc6 / sck / ispclk pc7 / ss pa3 v dd_1 v ss_1 (hs) 20ma high sink capability ei x associated external interrupt vector st72334j/n, st72314j/n, st72124j 10/153 pin description (contd) for external pin connection guidelines, refer to section 16 "electrical characteristics" on page 107 . legend / abbreviations for table 1 : type: i = input, o = output, s = supply input level: a = dedicated analog input in/output level: c = cmos 0.3v dd /0.7v dd , c t = cmos 0.3v dd /0.7v dd with input trigger output level: hs = 20ma high sink (on n-buffer only) port and control configuration: C input: float = floating, wpu = weak pull-up, int = interrupt 1) , ana = analog C output: od = open drain 2) , pp = push-pull refer to section 12 "i/o ports" on page 39 for more details on the software configuration of the i/o ports. the reset configuration of each pin is shown in bold. this configuration is valid as long as the device is in reset state. table 1. device pin description pin n pin name type level port main function (after reset) alternate function tqfp64 sdip56 qfp44 sdip42 input output input output float wpu int ana od pp 1 49 pe4 (hs) i/o c t hs x x x x port e4 2 50 pe5 (hs) i/o c t hs x x x x port e5 3 51 pe6 (hs) i/o c t hs x x x x port e6 4 52 pe7 (hs) i/o c t hs x x x x port e7 5 53 2 39 pb0 i/o c t x ei2 x x port b0 6 54 3 40 pb1 i/o c t x ei2 x x port b1 7 55 4 41 pb2 i/o c t x ei2 x x port b2 8 56 5 42 pb3 i/o c t x ei2 x x port b3 9 1 6 1 pb4 i/o c t x ei3 x x port b4 10 2 pb5 i/o c t x ei3 x x port b5 11 3 pb6 i/o c t x ei3 x x port b6 12 4 pb7 i/o c t x ei3 x x port b7 13 5 7 2 pd0/ain0 i/o c t x x x x x port d0 adc analog input 0 14 6 8 3 pd1/ain1 i/o c t x x x x x port d1 adc analog input 1 15 7 9 4 pd2/ain2 i/o c t x x x x x port d2 adc analog input 2 16 8 10 5 pd3/ain3 i/o c t x x x x x port d3 adc analog input 3 17 9 11 6 pd4/ain4 i/o c t x x x x x port d4 adc analog input 4 18 10 12 7 pd5/ain5 i/o c t x x x x x port d5 adc analog input 5 19 11 pd6/ain6 i/o c t x x x x x port d6 adc analog input 6 20 12 pd7/ain7 i/o c t x x x x x port d7 adc analog input 7 21 13 13 8 v dda s analog power supply voltage 22 14 14 9 v ssa s analog ground voltage 23 v dd_3 s digital main supply voltage st72334j/n, st72314j/n, st72124j 11/153 24 v ss_3 s digital ground voltage 25 15 15 10 pf0/mco i/o c t x ei1 x x port f0 main clock output (f osc /2) 26 16 16 11 pf1/beep i/o c t x ei1 x x port f1 beep signal output 27 17 17 12 pf2 i/o c t x ei1 x x port f2 28 nc not connected 29 18 18 13 pf4/ocmp1_a i/o c t x x x x port f4 timer a output compare 1 30 nc not connected 31 19 19 14 pf6 (hs)/icap1_a i/o c t hs x x x x port f6 timer a input capture 1 32 20 20 15 pf7 (hs)/extclk_a i/o c t hs x x x x port f7 timer a external clock source 33 21 21 v dd_0 s digital main supply voltage 34 22 22 v ss_0 s digital ground voltage 35 23 23 16 pc0/ocmp2_b i/o c t x x x x port c0 timer b output compare 2 36 24 24 17 pc1/ocmp1_b i/o c t x x x x port c1 timer b output compare 1 37 25 25 18 pc2 (hs)/icap2_b i/o c t hs x x x x port c2 timer b input capture 2 38 26 26 19 pc3 (hs)/icap1_b i/o c t hs x x x x port c3 timer b input capture 1 39 27 27 20 pc4/miso i/o c t x x x x port c4 spi master in / slave out data 40 28 28 21 pc5/mosi i/o c t x x x x port c5 spi master out / slave in data 41 29 29 22 pc6/sck i/o c t x x x x port c6 spi serial clock 42 30 30 23 pc7/ss i/o c t x x x x port c7 spi slave select (active low) 43 31 pa0 i/o c t x ei0 x x port a0 44 32 pa1 i/o c t x ei0 x x port a1 45 33 pa2 i/o c t x ei0 x x port a2 46 34 31 24 pa3 i/o c t x ei0 x x port a3 47 35 32 25 v dd_1 s digital main supply voltage 48 36 33 26 v ss_1 s digital ground voltage 49 37 34 27 pa4 (hs) i/o c t hs x x x x port a4 50 38 35 28 pa5 (hs) i/o c t hs x x x x port a5 51 39 36 29 pa6 (hs) i/o c t hs x t port a6 52 40 37 30 pa7 (hs) i/o c t hs x t port a7 53 41 38 31 ispsel i must be tied low in user mode. in pro- gramming mode when available, this pin acts as in-situ programming mode se- lection. 54 42 39 32 reset i/o c x x top priority non maskable interrupt (ac- tive low) 55 nc not connected 56 nc 57 43 40 33 v ss_3 s digital ground voltage 58 44 41 34 osc2 3) o resonator oscillator inverter output or capacitor input for rc oscillator pin n pin name type level port main function (after reset) alternate function tqfp64 sdip56 qfp44 sdip42 input output input output float wpu int ana od pp st72334j/n, st72314j/n, st72124j 12/153 notes : 1. in the interrupt input column, ei x defines the associated external interrupt vector. if the weak pull-up column (wpu) is merged with the interrupt column (int), then the i/o configuration is pull-up interrupt input, else the configuration is floating interrupt input. 2. in the open drain output column, t defines a true open drain i/o (p-buffer and protection diode to v dd are not implemented). see section 12 "i/o ports" on page 39 and section 16.8 "i/o port pin char- acteristics" on page 128 for more details. 3. osc1 and osc2 pins connect a crystal or ceramic resonator, an external rc, or an external source to the on-chip oscillator see section 3 "pin description" on page 7 and section 16.5 "clock and tim- ing characteristics" on page 116 for more details. 59 45 42 35 osc1 3) i external clock input or resonator oscilla- tor inverter input or resistor input for rc oscillator 60 46 43 36 v dd_3 s digital main supply voltage 61 47 44 37 pe0/tdo i/o c t x x x x port e0 sci transmit data out 62 48 1 38 pe1/rdi i/o c t x x x x port e1 sci receive data in 63 nc not connected 64 nc pin n pin name type level port main function (after reset) alternate function tqfp64 sdip56 qfp44 sdip42 input output input output float wpu int ana od pp st72334j/n, st72314j/n, st72124j 13/153 4 register & memory map as shown in the figure 5 , the mcu is capable of addressing 64k bytes of memories and i/o regis- ters. the available memory locations consist of 128 bytes of register locations, 384 or 512 bytes of ram, up to 256 bytes of data eeprom and 4 or 8 kbytes of user program memory. the ram space includes up to 256 bytes for the stack from 0100h to 01ffh. the highest address bytes contain the user reset and interrupt vectors. important: memory locations marked as re- served must never be accessed. accessing a re- served area can have unpredictable effects on the device. figure 5. memory map 0000h interrupt & reset vectors hw registers 027fh 0080h 16-bit addressing ram 007fh 0200h / 0280h 0bffh reserved 0080h (see table 2 ) 0c00h ffdfh ffe0h ffffh (see table 5 on page 34 ) 027fh c000h reserved 256 bytes data eeprom 0cffh 0d00h bfffh 00ffh 0100h 01ffh 0200h 8k bytes e000h 16k bytes program short addressing ram zero page 0080h 00ffh 01ffh 01ffh 384 bytes ram 512 bytes ram stack or 16-bit addressing ram 0100h memory program memory 8 kbytes e000h c000h 16 kbytes ffffh (128 bytes) (256 bytes) short addressing ram zero page stack or 16-bit addressing ram (128 bytes) (256 bytes) st72334j/n, st72314j/n, st72124j 14/153 register & memory map (contd) table 2. hardware register map address block register label register name reset status remarks 0000h 0001h 0002h port a padr paddr paor port a data register port a data direction register port a option register 00h 1) 00h 00h r/w r/w r/w 2) 0003h reserved area (1 byte) 0004h 0005h 0006h port c pcdr pcddr pcor port c data register port c data direction register port c option register 00h 1) 00h 00h r/w r/w r/w 0007h reserved area (1 byte) 0008h 0009h 000ah port b pbdr pbddr pbor port b data register port b data direction register port b option register 00h 1) 00h 00h r/w r/w r/w 2) 000bh reserved area (1 byte) 000ch 000dh 000eh port e pedr peddr peor port e data register port e data direction register port e option register 00h 1) 00h 00h r/w r/w r/w 2) 000fh reserved area (1 byte) 0010h 0011h 0012h port d pddr pdddr pdor port d data register port d data direction register port d option register 00h 1) 00h 00h r/w r/w r/w 2) 0013h reserved area (1 byte) 0014h 0015h 0016h port f pfdr pfddr pfor port f data register port f data direction register port f option register 00h 1) 00h 00h r/w r/w r/w 0017h to 001fh reserved area (9 bytes) 0020h miscr1 miscellaneous register 1 00h r/w 0021h 0022h 0023h spi spidr spicr spisr spi data i/o register spi control register spi status register xxh 0xh 00h r/w r/w read only 0024h to 0028h reserved area (5 bytes) 0029h mcc mccsr main clock control / status register 01h r/w st72334j/n, st72314j/n, st72124j 15/153 002ah watchdog wdgcr watchdog control register 7fh r/w 002bh crsr clock, reset, supply control / status register 000x 000x r/w 002ch data-eeprom eecsr data-eeprom control/status register 00h r/w 002dh 0030h reserved area (4 bytes) 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003ah 003bh 003ch 003dh 003eh 003fh timer a tacr2 tacr1 tasr taic1hr taic1lr taoc1hr taoc1lr tachr taclr taachr taaclr taic2hr taic2lr taoc2hr taoc2lr timer a control register 2 timer a control register 1 timer a status register timer a input capture 1 high register timer a input capture 1 low register timer a output compare 1 high register timer a output compare 1 low register timer a counter high register timer a counter low register timer a alternate counter high register timer a alternate counter low register timer a input capture 2 high register timer a input capture 2 low register timer a output compare 2 high register timer a output compare 2 low register 00h 00h xxh xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w read only read only read only r/w r/w read only read only read only read only read only 3) read only 3) r/w 3) r/w 3) 0040h miscr2 miscellaneous register 2 00h r/w 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004ah 004bh 004ch 004dh 004eh 004fh timer b tbcr2 tbcr1 tbsr tbic1hr tbic1lr tboc1hr tboc1lr tbchr tbclr tbachr tbaclr tbic2hr tbic2lr tboc2hr tboc2lr timer b control register 2 timer b control register 1 timer b status register timer b input capture 1 high register timer b input capture 1 low register timer b output compare 1 high register timer b output compare 1 low register timer b counter high register timer b counter low register timer b alternate counter high register timer b alternate counter low register timer b input capture 2 high register timer b input capture 2 low register timer b output compare 2 high register timer b output compare 2 low register 00h 00h xxh xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w read only read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h sci scisr scidr scibrr scicr1 scicr2 scierpr scietpr sci status register sci data register sci baud rate register sci control register 1 sci control register 2 sci extended receive prescaler register reserved area sci extended transmit prescaler register c0h xxh 00xx xxxx xxh 00h 00h --- 00h read only r/w r/w r/w r/w r/w r/w address block register label register name reset status remarks st72334j/n, st72314j/n, st72124j 16/153 legend : x=undefined, r/w=read/write notes : 1. the contents of the i/o port dr registers are readable only in output configuration. in input configura- tion, the values of the i/o pins are returned instead of the dr register contents. 2. the bits corresponding to unavailable pins are forced to 1 by hardware, affecting accordingly the reset status value. these bits must always keep their reset value. 3. external pin not available. 0058h 006fh reserved area (24 bytes) 0070h 0071h adc adcdr adccsr data register control/status register xxh 00h read only r/w 0072h to 007fh reserved area (14 bytes) address block register label register name reset status remarks st72334j/n, st72314j/n, st72124j 17/153 5 flash program memory 5.1 introduction flash devices have a single voltage non-volatile flash memory that may be programmed in-situ (or plugged in a programming tool) on a byte-by- byte basis. 5.2 main features n remote in-situ programming (isp) mode n up to 16 bytes programmed in the same cycle n mtp memory (multiple time programmable) n read-out memory protection against piracy 5.3 structural organisation the flash program memory is organised in a single 8-bit wide memory block which can be used for storing both code and data constants. the flash program memory is mapped in the up- per part of the st7 addressing space and includes the reset and interrupt user vector area . 5.4 in-situ programming (isp) mode the flash program memory can be programmed using remote isp mode. this isp mode allows the contents of the st7 program memory to be up- dated using a standard st7 programming tools af- ter the device is mounted on the application board. this feature can be implemented with a minimum number of added components and board area im- pact. an example remote isp hardware interface to the standard st7 programming tool is described be- low. for more details on isp programming, refer to the st7 programming specification. remote isp overview the remote isp mode is initiated by a specific se- quence on the dedicated ispsel pin. the remote isp is performed in three steps: C selection of the ram execution mode C download of remote isp code in ram C execution of remote isp code in ram to pro- gram the user program into the flash remote isp hardware configuration in remote isp mode, the st7 has to be supplied with power (v dd and v ss ) and a clock signal (os- cillator and application crystal circuit for example). this mode needs five signals (plus the v dd signal if necessary) to be connected to the programming tool. this signals are: C reset : device reset Cv ss : device ground power supply C ispclk: isp output serial clock pin C ispdata: isp input serial data pin C ispsel: remote isp mode selection. this pin must be connected to v ss on the application board through a pull-down resistor. if any of these pins are used for other purposes on the application, a serial resistor has to be imple- mented to avoid a conflict if the other device forces the signal level. figure 6 shows a typical hardware interface to a standard st7 programming tool. for more details on the pin locations, refer to the device pinout de- scription. figure 6. typical remote isp interface 5.5 memory read-out protection the read-out protection is enabled through an op- tion bit. for flash devices, when this option is selected, the program and data stored in the flash memo- ry are protected against read-out piracy (including a re-write protection). when this protection option is removed the entire flash program memory is first automatically erased. however, the e 2 prom data memory (when available) can be protected only with rom devices. ispsel v ss reset ispclk ispdata osc1 osc2 v dd st7 he10 connector type to programming tool 10k w c l0 c l1 application 47k w 1 xtal st72334j/n, st72314j/n, st72124j 18/153 6 data eeprom 6.1 introduction the electrically erasable programmable read only memory can be used as a non volatile back- up for storing data. using the eeprom requires a basic access protocol described in this chapter. 6.2 main features n up to 16 bytes programmed in the same cycle n eeprom mono-voltage (charge pump) n chained erase and programming cycles n internal control of the global programming cycle duration n end of programming cycle interrupt flag n wait mode management figure 7. eeprom block diagram eecsr eeprom interrupt falling edge high voltage pump ie lat 0 0 0 0 0 pgm eeprom reserved detector eeprom memory matrix (1 row = 16 x 8 bits) address decoder data multiplexer 16 x 8 bits data latches row decoder data bus 4 4 4 128 128 address bus st72334j/n, st72314j/n, st72124j 19/153 data eeprom (contd) 6.3 memory access the data eeprom memory read/write access modes are controlled by the lat bit of the eep- rom control/status register (eecsr). the flow- chart in figure 8 describes these different memory access modes. read operation (lat=0) the eeprom can be read as a normal rom loca- tion when the lat bit of the eecsr register is cleared. in a read cycle, the byte to be accessed is put on the data bus in less than 1 cpu clock cycle. this means that reading data from eeprom takes the same time as reading data from eprom, but this memory cannot be used to exe- cute machine code. write operation (lat=1) to access the write mode, the lat bit has to be set by software (the pgm bit remains cleared). when a write access to the eeprom area occurs, the value is latched inside the 16 data latches ac- cording to its address. when pgm bit is set by the software, all the previ- ous bytes written in the data latches (up to 16) are programmed in the eeprom cells. the effective high address (row) is determined by the last eep- rom write sequence. to avoid wrong program- ming, the user must take care that all the bytes written between two programming sequences have the same high address: only the four least significant bits of the address can change. at the end of the programming cycle, the pgm and lat bits are cleared simultaneously, and an inter- rupt is generated if the ie bit is set. the data eep- rom interrupt request is cleared by hardware when the data eeprom interrupt vector is fetched. note : care should be taken during the program- ming cycle. writing to the same memory location will over-program the memory (logical and be- tween the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the fa lling edge of lat bit. it is not possible to read the latched data. this note is ilustrated by the figure 9 . figure 8. data eeprom programming flowchart read mode lat=0 pgm=0 write mode lat=1 pgm=0 read bytes in eeprom area writeupto16bytes in eeprom area (with the same 11 msb of the address) start programming cycle lat=1 pgm=1 (set by software) lat interrupt generation if ie=1 0 1 cleared by hardware st72334j/n, st72314j/n, st72124j 20/153 data eeprom (contd) 6.4 power saving modes wait mode the data eeprom can enter wait mode on ex- ecution of the wfi instruction of the microcontrol- ler. the data eeprom will immediately enter this mode if there is no programming in progress, otherwise the data eeprom will finish the cycle and then enter wait mode. halt mode the data eeprom immediatly enters halt mode if the microcontroller executes the halt in- struction. therefore the eeprom will stop the function in progress, and data may be corrupted. 6.5 access error handling if a read access occurs while lat=1, then the data bus will not be driven. if a write access occurs while lat=0, then the data on the bus will not be latched. if a programming cycle is interrupted (by software/ reset action), the memory data will not be guar- anteed. figure 9. data eeprom programming cycle lat erase cycle write cycle pgm t prog read operation not possible write of data latches read operation possible internal programming voltage eeprom interrupt st72334j/n, st72314j/n, st72124j 21/153 data eeprom (contd) 6.6 register description control/status register (csr) read/write reset value: 0000 0000 (00h) bit 7:3 = reserved, forced by hardware to 0. bit 2 = ie interrupt enable this bit is set and cleared by software. it enables the data eeprom interrupt capability when the pgm bit is cleared by hardware. the interrupt request is automatically cleared when the software enters the interrupt routine. 0: interrupt disabled 1: interrupt enabled bit 1 = lat latch access transfer this bit is set by software. it is cleared by hard- ware at the end of the programming cycle. it can only be cleared by software if pgm bit is cleared. 0: read mode 1: write mode bit 0 = pgm programming control and status this bit is set by software to begin the programming cycle. at the end of the programming cycle, this bit is cleared by hardware and an interrupt is generated if the ite bit is set. 0: programming finished or not yet started 1: programming cycle is in progress note : if the pgm bit is cleared during the program- ming cycle, the memory data is not guaranteed 70 00000ielatpgm st72334j/n, st72314j/n, st72124j 22/153 7 data eeprom register map and reset values 7.1 read-out protection option the data eeprom can be optionally read-out protected in st72334 rom devices (see option list on page 146 ). st72c334 flash devices do not have this protection option. address (hex.) register label 76543210 002ch eecsr reset value 00000 ie 0 rwm 0 pgm 0 st72334j/n, st72314j/n, st72124j 23/153 8 central processing unit 8.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 8.2 main features n 63 basic instructions n fast 8-bit by 8-bit multiply n 17 main addressing modes n two 8-bit index registers n 16-bit stack pointer n low power modes n maskable hardware interrupts n non-maskable software interrupt 8.3 cpu registers the 6 cpu registers shown in figure 10 are not present in the memory mapping and are accessed by specific instructions. accumulator (a) the accumulator is an 8-bit general purpose reg- ister used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. index registers (x and y) in indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (the cross-assembler generates a precede in- struction (pre) to indicate that the following in- struction refers to the y register.) the y register is not affected by the interrupt auto- matic procedures (not pushed to and popped from the stack). program counter (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers pcl (program counter low which is the lsb) and pch (program counter high which is the msb). figure 10. cpu registers accumulator x index register y index register stack pointer condition code register program counter 70 1c 11hi nz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 8 70 reset value = stack higher address reset value = 1x 11x1xx reset value = xxh reset value = xxh reset value = xxh x = undefined value st72334j/n, st72314j/n, st72124j 24/153 cpu registers (contd) condition code register (cc) read/write reset value: 111x1xxx the 8-bit condition code register contains the in- terrupt mask and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop in- structions. these bits can be individually tested and/or con- trolled by specific instructions. bit 4 = h half carry . this bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the alu during an add or adc instruction. it is reset by hardware during the same instructions. 0: no half carry has occurred. 1: a half carry has occurred. this bit is tested using the jrh or jrnh instruc- tion. the h bit is useful in bcd arithmetic subrou- tines. bit 3 = i interrupt mask . this bit is set by hardware when entering in inter- rupt or by software to disable all interrupts except the trap software interrupt. this bit is cleared by software. 0: interrupts are enabled. 1: interrupts are disabled. this bit is controlled by the rim, sim and iret in- structions and is tested by the jrm and jrnm in- structions. note: interrupts requested while i is set are latched and can be processed when i is cleared. by default an interrupt routine is not interruptable because the i bit is set by hardware at the start of the routine and reset by the iret instruction at the end of the routine. if the i bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the cur- rent interrupt routine. bit 2 = n negative . this bit is set and cleared by hardware. it is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. it is a copy of the 7 th bit of the result. 0: the result of the last operation is positive or null. 1: the result of the last operation is negative (i.e. the most significant bit is a logic 1). this bit is accessed by the jrmi and jrpl instruc- tions. bit 1 = z zero . this bit is set and cleared by hardware. this bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: the result of the last operation is different from zero. 1: the result of the last operation is zero. this bit is accessed by the jreq and jrne test instructions. bit 0 = c carry/borrow. this bit is set and cleared by hardware and soft- ware. it indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: no overflow or underflow has occurred. 1: an overflow or underflow has occurred. this bit is driven by the scf and rcf instructions and tested by the jrc and jrnc instructions. it is also affected by the bit test and branch, shift and rotate instructions. 70 111hinzc st72334j/n, st72314j/n, st72124j 25/153 central processing unit (contd) stack pointer (sp) read/write reset value: 01 ffh the stack pointer is a 16-bit register which is al- ways pointing to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see figure 11 ). since the stack is 256 bytes deep, the 8th most significant bits are forced by hardware. following an mcu reset, or after a reset stack pointer in- struction (rsp), the stack pointer contains its re- set value (the sp7 to sp0 bits are set) which is the stack higher address. the least significant byte of the stack pointer (called s) can be directly accessed by a ld in- struction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, with- out indicating the stack overflow. the previously stored information is then overwritten and there- fore lost. the stack also wraps in case of an under- flow. the stack is used to save the return address dur- ing a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instruc- tions. in the case of an interrupt, the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations as shown in figure 11 . C when an interrupt is received, the sp is decre- mented and the context is pushed on the stack. C on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an in- terrupt five locations in the stack area. figure 11. stack manipulation example 15 8 00000001 70 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 01ffh @ 0100h stack higher address = 01ffh stack lower address = 0100h st72334j/n, st72314j/n, st72124j 26/153 9 supply, reset and clock management the st72334j/n, st72314j/n and st72124j mi- crocontrollers include a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing the number of external components. an overview is shown in figure 12 . see section 16 "electrical characteris- tics" on page 107 for more details. main features n supply manager with main supply low voltage detection (lvd) n reset sequence manager (rsm) n multi-oscillator (mo) C 4 crystal/ceramic resonator oscillators C 1 external rc oscillator C 1 internal rc oscillator n clock security system (css) Cclock filter C backup safe oscillator figure 12. clock, reset and supply block diagram ie d 0 0 0 0 rf rf crsr css wdg f osc css interrupt lvd low voltage detector (lvd) multi- oscillator (mo) from watchdog peripheral osc1 reset vdd vss reset sequence manager (rsm) clock filter safe osc clock security system (css) osc2 to main clock controller st72334j/n, st72314j/n, st72124j 27/153 9.1 low voltage detector (lvd) to allow the integration of power management features in the application, the low voltage detec- tor function (lvd) generates a static reset when the v dd supply voltage is below a v it- reference value. this means that it secures the power-up as well as the power-down keeping the st7 in reset. the v it- reference value for a voltage drop is lower than the v it+ reference value for power-on in order to avoid a parasitic reset when the mcu starts run- ning and sinks current on the supply (hysteresis). the lvd reset circuitry generates a reset when v dd is below: Cv it+ when v dd is rising Cv it- when v dd is falling the lvd function is illustrated in the figure 13 . provided the minimum v dd value (guaranteed for the oscillator frequency) is above v it- , the mcu can only be in two modes: C under full software control C in static safe reset in these conditions, secure operation is always en- sured for the application without the need for ex- ternal reset hardware. during a low voltage detector reset, the r eset pin is held low, thus permitting the mcu to reset other devices. notes : 1. the lvd allows the device to be used without any external reset circuitry. 2. three different reference levels are selectable through the option byte according to the applica- tion requirement. lvd application note application software can detect a reset caused by the lvd by reading the lvdrf bit in the crsr register. this bit is set by hardware when a lvd reset is generated and cleared by software (writing zero). figure 13. low voltage detector vs reset v dd v it+ reset v it- v hyst st72334j/n, st72314j/n, st72124j 28/153 9.2 reset sequence manager (rsm) 9.2.1 introduction the reset sequence manager includes three re- set sources as shown in figure 15 : n external reset source pulse n internal lvd reset (low voltage detection) n internal watchdog reset these sources act on the reset pin and it is al- ways kept low during the delay phase. the reset service routine vector is fixed at ad- dresses fffeh-ffffh in the st7 memory map. the basic reset sequence consists of 3 phases as shown in figure 14 : n delay depending on the reset source n 4096 cpu clock cycle delay n reset vector fetch the 4096 cpu clock cycle delay allows the oscil- lator to stabilise and ensures that recovery has taken place from the reset state. the reset vector fetch phase duration is 2 clock cycles. figure 14. reset sequence phases figure 15. reset block diagram reset delay internal reset 4096 clock cycles fetch vector f cpu counter reset r on v dd watchdog reset lvd reset internal reset st72334j/n, st72314j/n, st72124j 29/153 reset sequence manager (contd) 9.2.2 asynchronous external reset pin the reset pin is both an input and an open-drain output with integrated r on weak pull-up resistor. this pull-up has no fixed value but varies in ac- cordance with the input voltage. it can be pulled low by external circuitry to reset the device. see electrical characteristics section for more details. a reset signal originating from an external source must have a duration of at least t h(rstl)in in order to be recognized. this detection is asynchro- nous and therefore the mcu can enter reset state even in halt mode. the reset pin is an asynchronous signal which plays a major role in ems performance. in a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteris- tics section. two reset s equences can be associated with this reset source: short or long external reset pulse (see figure 16 ). starting from the external reset pulse recogni- tion, the device reset pin acts as an output that is pulled low during at least t w(rstl)out . 9.2.3 internal low voltage detection reset two different reset s equences caused by the in- ternal lvd circuitry can be distinguished: n power-on reset n voltage drop r eset the device reset pin acts as an output that is pulled low when v dd |